The present invention relates to a logic simulation apparatus for simulating the operation of a logic circuit.
Conventionally, the operation of a logic circuit is programmed by software of a general large computer so as to simulate the operation of the logic circuit. A table-driven algorithm, as described in "Digital Logic Simulation In a Time-Based, Table-Driven Environment Part 1. Design Verification" by S. A. Szygenda and E. W. Thompson, Computer PP. 24-36, March 1975, is well-known as software simulation of this type. According to this algorithm, module data are stored in tables, and tables are selectively read out in accordance with the relationship of interconnections of the modules. The data (i.e., data constituting the corresponding table) of each module include module function data (AND, OR, etc.), interconnection data, input/output data, etc.
In the software simulation described above, the processing time per one logic module for data transfer, data processing, etc. is considerably longer than the operation time of the actual module. For this reason, the simulation time is increased in accordance with an increase in a circuit scale, resulting in inconvenience.